Research Bits: Aug. 18

Edge AI hardware/algorithm co-design

Researchers from the University of Massachusetts Amherst and TetraMem combined memristive analog in-memory computing hardware with hyperdimensional computing algorithms to improve AI edge device efficiency.

Hyperdimensional computing represents information using large mathematical patterns instead of working with precise numbers. The platform can both encode language features and process language identification.

“The encoding part leverages the intrinsic randomness of memristive devices, considered by many to be a drawback for this device technology,” said Qiangfei Xia, professor of electrical and computer engineering and head of the Nanodevices and Integrated Systems Lab in the UMass Riccio College of Engineering, in a press release. “We demonstrated written language processing in this work; we believe it will also be capable of spoken language processing, leading to energy-efficient natural language processing on edge devices such as phones, speakers, cars, robots, etc.”

As proof of concept, their system achieved 95.24% accuracy in language identification. The researchers have also used the chip for RF signal processing, sensing, and wireless receivers. [1]

Memtransistor with programmable response speeds​

Researchers from the Korea Advanced Institute of Science and Technology (KAIST) designed a programmable dynamic memtransistor (PDM) for processing time-series signals, with potential applications for real-time AI.

“This study demonstrates an AI semiconductor whose response characteristics can be programmed to efficiently process data changing at different speeds,” said Shinhyun Choi, chair professor from the School of Electrical Engineering and the Graduate School of Semiconductor Technology at KAIST, in a statement. “We expect it to become a core technology that improves the performance of AI devices such as autonomous vehicles, robots, and wearables while reducing their power consumption.”

The transistor has a dual-layer structure that combines a charge storage layer that accumulates and processes data with an electron trapping layer that controls the response speed in a nonvolatile manner. Incoming data is processed in the charge storage layer, while the electron trapping layer controls, across multiple levels, the recovery speed at which the semiconductor returns to its original state. In experiments, the team was able to tune the current recovery time over an approximately 5-fold range and the characteristic frequency over a range of more than 10-fold. Compared with conventional fixed-response semiconductor devices, it reduced prediction errors by up to 40 times for time-varying data. [2]

Artificial synapse with long- and short-term memory

Researchers from Sungkyunkwan University, Ajou University, University of Tokyo, and Hanyang University developed a neuromorphic semiconductor device that independently implements long-term and short-term memory using surface acoustic waves (SAWs) as a control signal.

The reconfigurable artificial synapse integrates a monolayer molybdenum disulfide (MoS₂) memristor and a SAW device onto a single platform. Electrical signals are used to form long-term memory, while SAWs are used to control short-term memory through a non-contact mechanism, enabling it to be selectively generated and erased without damaging long-term memory.

Biological short-term synaptic plasticity was reproduced by adjusting the intensity, pulse width, and interval of the SAWs. The device maintained stable operation without performance degradation even after more than 10,000 seconds of repeated operation and achieved a recognition accuracy of 96.1% in a character classification task when applied to reservoir computing. [3]

References

[1] Y. Huang, A.J. Rad, D. Belkin, et al. Hyperdimensional in-memory computing with analogue memristive crossbar arrays. Nat Commun (2026). https://doi.org/10.1038/s41467-026-76067-5

[2] Dw. Kim, Y. Cho, S. Seo, et al. Programmable memtransistor array with temporal dynamics modulation for efficient time-series data processing. Nat Commun 17, 8311 (2026). https://doi.org/10.1038/s41467-026-75211-5

[3] S. Kim, J. W. Lee, H. Ryu, et al. Surface Acoustic Wave-Guided Reconfigurable Memristor. ACS Nano 28 July 2026; 20 (29): 20530–20542. https://doi.org/10.1021/acsnano.6c01958

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