By Dana Neustadter and Ilya Tolchinsky Artificial intelligence is moving beyond digital experiences and into systems that interact directly with the physical world.…
This emerging category of physical AI spans autonomous vehicles that e…
Unlike conventional AI applications, these systems must do more than p…
Continuing A Legacy Of Space Exploration: NASA’s Nancy Grace Roman Space Telescope
This month, we are celebrating the launch of NASA’s Nancy Grace Roman Space Telescope, a flagship mission to explore the universe’s greatest mysteries.…
Designed to investigate dark energy, dark matter, and planets beyond o…
With its powerful infrared imaging capabilities and expansive field of…
How Many Design Experiments Does A Machine Learning Predictor Actually Need?
Machine learning prediction in CAE has a clear proposition: Train a predictor on solved design experiments, then evaluate new designs in seconds instead of hours.…
The proposition is only as good as the training dataset, and the datas…
Every design experiment is a full, explicit crash run.
Key Takeaways: With AI-driven demand for data center capacity making data center security more crucial than ever, the convergence of physical and cybersecurity can no longer be an afterthought.…
The boundaries of trust must expand to cover the entire supply chain, …
New security standards for data center components are driving componen…
Key Takeaways: Distributed compute includes AI-enabled MCUs/NPUs in the palm of the hand to pre-process finger data, while a centralized compute system often features a GPU to process the raw inputs from all sensors via an FPGA-based sensor bridge and Ethernet.…
Hybrid architectures are needed to accommodate various robotics applic…
Others will benefit from targeted small language models.
Protecting Mission-Critical Data Beyond The SoC: Why Inline Memory Encryption Needs Integrity
By Vincent van der Leest and Ajay Kapoor Security architects devote considerable attention to trusted processing, secure boot, and protected communications.…
Yet sensitive instructions and data often leave the system-on-chip (So…
That interface can expose mission-critical data like cryptographic mat…
Cadence’s Udaya Shankar explores the major shifts shaping the transformation of modern semiconductor design, from transistor architecture evolution and manufacturing complexity to chiplet-based design, UCIe standardization, and high-bandwidth memory.…
In a podcast, Siemens’ Tova Levy chats with Sudarshan Deo about what A…
Synopsys’ Sudeep Shivalli highlights stronger government support, expa…
Extending 18A With Significant Power And Performance Gains
With Intel 18A, Intel Foundry introduced industry-first technologies with RibbonFET Gate-all-around (GAA) transistor architecture and PowerVia backside power delivery in a production-ready process designed for high-volume manufacturing.…
Intel 18A-P, the first performance-enhanced node in the Intel 18A fami…
² In research presented at the 2026 IEEE/JSAP Symposium on VLSI Techno…
Security Sign-Off Is Coming For Chips — But Standards May Not Be Enough
Key Takeaways: AI is emerging as a force multiplier for cryptanalysis, increasing pressure on post-quantum implementations even if lattice-based algorithms remain broadly trusted.…
Security sign-off is becoming inevitable, but experts say it must be p…
The industry’s move toward heterogeneous systems, custom AI hardware, …
Cadence’s Udaya Shankar explores the major shifts shaping the transformation of modern semiconductor design, from transistor architecture evolution and manufacturing complexity to chiplet-based design, UCIe standardization, and high-bandwidth memory.…
In a podcast, Siemens’ Tova Levy chats with Sudarshan Deo about what A…
Synopsys’ Sudeep Shivalli highlights stronger government support, expa…
The Evolution Of Intelligent Systems: From Optimization To Automation to AI
Traditional approaches to signal and power integrity analysis are insufficient, prompting a shift toward integrated systems that enhance decision-making, execution, and adaptability.…
This white paper frames this shift as an evolution across three interc…
EBook – Accelerate Silicon Design for Physical AI (Part 1)
Physical AI demands more than traditional edge silicon.Devices must perceive, reason, and act in real time while protecting data and scaling across product lines.…
This eBook shows how to move from concept to production while reducing…
What You Will Learn: Realizing Physical AI spans architecture, IP sele…
New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations Thermal Tuning Overhead in Wafer-Scale Optical Interconnects for LLM MoE Training: A Cross-Layer Analysis and Ferroelectric-Based Mitigation Georgia Tech ROBBIN: Rowhammer-Based Backdoor Injection during Inference Northeastern University An Open-Source Benchmark Suite of 3D-IC Testcases UCLA Generative Design of Liquid-Cooling Channels for Thermal Management of 2.…
5D and 3D Integrated Advanced Packaging University of Michigan-Dearbor…
Deep Learning to Automate Parameter Extraction and Model Fitting of Tw…
High-voltage GaN Researchers from Ecole Polytechnique Fédérale de Lausanne (EPFL) debuted a new class of gallium nitride (GaN) transistor, called an intrinsic polarization superjunction (iPSJ), that can handle very high voltage with minimal energy loss.…
Made from layers of GaN on a low-cost silicon base, the iPSJ can withs…
“We achieve this by exploiting a natural polarization effect that is u…
Advancing The CFET-Based Device Roadmap: Novel Integration Modules And Standard Cell Configurations
By Cassie Sheng, Hiroaki Arimura, and Naoto Horiguchi Key takeaways: From the A7 logic technology node onwards, industry may likely transition to CFET-based transistor architectures which enable 4.…
5T) and below standard cells.
Progress in CFET enablement is backed by two complementary R&D tracks,…
Workload-Driven HBF Substrate For Capacity-Scalable LLM Inference (Huawei, ETH Zurich, HUST)
Researchers at Huawei, ETH Zürich, and HUST published a technical paper titled “FLINT: Efficiently Leveraging High Bandwidth Flash for Capacity-Scalable LLM Inference Acceleration.…
” Abstract: “LLM inference is increasingly constrained by accelerator …
This constraint is especially acute in single-accelerator and small-no…
Key Takeaways: Photonics changes chiplet design from a placement problem into a multi-physics co-design problem because thermal, mechanical, electromagnetic, and optical effects interact bidirectionally.…
The closer optical chiplets move to compute silicon, the more bandwidt…
Chip architects should start with traffic patterns, system architectur…
Molecular Dynamics Study Explains Aluminum Dopant Activation In 4H-SiC (TU Wien, Silvaco)
Researchers from TU Wien and Silvaco Europe published a technical paper titled “The influence of implantation conditions on dopant activation in Al-implanted 4H-SiC: A MD study applying an Al potential fitted to DFT barriers.…
” Abstract Excerpt: “The non-monotonic dependence of Al dopant activat…
We present a molecular dynamics (MD) study of Al implantation in 4H-Si…
Cycle-Level Simulator for Distributed GPUs For AI Workloads (Purdue)
Researchers from Purdue University published a technical paper titled “Architecting the Next Generation of Asynchronous, Distributed GPUs for the AI Era.…
” Abstract Excerpt: The paper presents a “cycle-level simulation frame…
It also reports validation against physical silicon, including a “99% …
Intrinsic Polarization Superjunctions Boost GaN-On-Silicon Power Devices (EPFL)
Researchers from École Polytechnique Fédérale de Lausanne (EPFL) published a technical paper titled “Intrinsic polarization superjunctions in III-nitride heterostructures for efficient power electronics.…
” Abstract Excerpt: “III-nitride semiconductors combine a wide bandgap…
Their lateral architecture also enables monolithic integration on cost…
M3D 6T SRAM With BEOL Pass-Gates at 2nm (Georgia Tech, Synopsys)
Researchers from Georgia Institute of Technology and Synopsys published a technical paper titled “A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node.…
” Abstract Excerpt: The paper proposes “a monolithic-3D (M3D) 6T SRAM …
It also reports that the resulting cell “achieves a 25% footprint redu…
Hybrid HBM-HBF Architecture in LLM Inference (University of Oxford)
Researchers at the University of Oxford published a technical paper titled “Hardware-Managed Heterogeneous High-Bandwidth Memory and Flash in LLM Inference Systems.…