Sticker shock Gartner says AI inferencing costs per agentic workflow will increase fivefold through 2028, with the rate of innovation outpacing the cost curve.…
Samsung increased pricing on new 4nm, 5nm, and 8nm foundry orders by u…
Its Pyeongtaek 4nm line is reportedly running at full capacity.
Key Takeaways: Intel, Samsung, TSMC, and IBM are choosing different ways to connect nanosheet tiers, but all will use direct backside vias for backside power delivery.…
At the heart of CFETs are defect-free epitaxy, ALD dielectrics, workfu…
Virtual simulation speeds pathfinding, integration, and yield-improvem…
Three Strategic Imperatives For Energy-Efficient AI Computing
The headlines are dominated by the unprecedented growth in data centers and their rising energy consumption, along with the skyrocketing user cost of AI for inference at scale.…
Perhaps less obvious is the direct connection between the two – reduci…
This is because both require smart use of AI system capability at maxi…
Reducing Scope 3 Value Chain Emissions For Customers Through Sustainability And Innovation
As data center infrastructure expands to meet growing AI demand, sustainability is becoming an increasingly important consideration for Intel Foundry customers.…
Companies are evaluating not only energy consumption and carbon emissi…
From Research To Production: Collaboration Is Key For Semiconductor Innovation
As semiconductor technologies become more complex, competitive advantage increasingly depends on access to realistic development environments, silicon learning, and high-quality data.…
Turning research breakthroughs into production-ready solutions require…
Research organizations, foundries, equipment suppliers, software provi…
Don’t Scrap It, Save It: Feedforward Control For Modern Semiconductor Manufacturing
Semiconductor yield is a constant battle against process variability.Every wafer that falls out of spec represents lost time, lost capacity, and lost value.…
In advanced semiconductor manufacturing, even small shifts in critical…
Cadence’s Ravi Vora explains how the AMBA AXI5 Memory Tagging Extension can detect memory misuse with minimal runtime overhead by associating a small allocation tag with each memory granule and checking every pointer access against the expected tag.…
Synopsys’ Shawn Carpenter creates a digital twin of the Moon that comb…
In a podcast, Siemens’ Tova Levy chats with Bob Patti of NHanced Semic…
The Future Of AI Compute Won’t Run On Just One Kind Of Chip
Key Takeaways: Compute clusters bring different parallelization paradigms, such as Tensor parallel, data parallel, context parallel, and pipeline parallel, each with a different network topology requirement.…
Inference disaggregation means that one cluster has a specific set of …
In moving from training to inference, a heterogeneous cluster environm…
Edge AI hardware/algorithm co-design Researchers from the University of Massachusetts Amherst and TetraMem combined memristive analog in-memory computing hardware with hyperdimensional computing algorithms to improve AI edge device efficiency.…
Hyperdimensional computing represents information using large mathemat…
The platform can both encode language features and process language id…
Semiconductor Earnings Roundup: Revenue, Growth and Takeaways
Earnings were strong across all chip industry sectors this quarter, with 11 companies posting triple-digit growth, and all but 2 of the 80 companies reported here were in positive territory.…
The hottest growth areas were AI infrastructure, memory, advanced pack…
Companies tied to HBM, data centers and AI accelerators generally post…
New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations ReVolt: Power Delivery Network-Aware Voltage Droop Control for 2.…
5D PIM Chiplet Architectures Washington State University, University o…
imec From Lithography to Nanoimprint: Physics-Based, Data-Driven, and …
Controlling Voltage Droop In 2.5D PIM Chiplet Architectures (Washington St., UW-Madison)
Researchers from Washington State University and University of Wisconsin–Madison published a technical paper titled “ReVolt: Power Delivery Network-Aware Voltage Droop Control for 2.…
Key Takeaways: AI data centers use exponentially increasing amounts of power; the challenge now is converting high-voltage AC grid power to low-voltage chips that require DC.…
The 800VDC architecture for AI data centers is more efficient than 48V…
Packet-Based NPUs In The LLM Era: From Compute-Bound CNNs To Memory-Bound Edge And Automotive Workloads
Many Semiconductor Engineering readers know the basic story behind Expedera’s Origin NPU IP architecture: packets instead of layers, higher MAC utilization, and less gratuitous movement of activations to external memory.…
What’s changing now is the workload mix.
Vision-only edge processors are giving way to systems where LLMs, VLMs…
What Self-Verifying Means In Agentic EDA Workflows And Why It Matters
Last month, we covered the architectural decisions behind a production-ready EDA AI agent: domain grounding, scalable orchestration across a fragmented tool ecosystem, native interpretation of EDA data formats, and security at the execution layer.…
These are the foundations upon which successful agentic workflows for …
When an agent is executing a long-running EDA workflow autonomously, m…
Key Takeaways: Hardware and software development have traditionally been disconnected, creating little opportunity to optimize system-level performance and energy consumption.…
Development swings between specialized and generalized solutions based…
Energy and thermal concerns are forcing more companies to create speci…
Key Takeaways: The push toward 1-megawatt racks is forcing fundamental changes in data center architecture, including cooling, power delivery, rack design, and 3D-IC packaging.…
Higher rack densities may not be the only viable scaling path, as opti…
AI and agentic workloads are shifting systems from average-power assum…